1. Field of the Disclosure
The disclosed methods and systems relate to a semiconductor integrated circuit and, more particularly, to a non-volatile memory device with a redundancy selector circuit.
2. Discussion of Related Art
Memory devices are integrated circuits capable of storing and later retrieving data. Generally, a memory device includes a plurality of memory cells each storing one or more bits of data. Unfortunately, memory cells may be defective due to a number of reasons, such as an unstable fabrication process or degradation resulting from lapse of time. Accordingly, a given memory device may not ever operate properly and/or its reliability may deteriorate over time.
However, in order to increase production yield, many approaches have been devised to overcome problems caused by infrequent defective memory cells without altogether discarding the memory devices containing the defects. One of these approaches is to incorporate redundancy circuits in a memory device. The redundancy circuits generally have a plurality of defect-free memory cells to logically (not physically) replace known defective memory cells. Exemplary redundancy circuits are disclosed in U.S. Pat. No. 6,118,712 entitled “REDUNDANCY FUSE BOXES AND REDUNDANCY REPAIR STRUCTURES FOR SEMICONDUCTOR DEVICES” and U.S. Pat. No. 6,850,450 entitled “FUSE BOX INCLUDING MAKE-LINK AND REDUNDANT ADDRESS DECODER HAVING THE SAME AND METHOD FOR REPAIRING DEFECTIVE MEMORY CELL”, both of which are incorporated herein by reference in their entirety.
Redundancy circuits often store addresses of defective memory cells in a fuse circuit by selectively cutting fuses within the fuse circuit. Accordingly, during normal operation of the memory device using the redundancy circuits, addresses input to the memory device (or addresses generated internally) are compared to each stored defective memory address and, based on the comparison result, a redundant memory cell may be selected in place of a defective memory cell.
Unfortunately, a shortfall of this form of memory repair arises when the operating speed of the memory device inadvertently causes a defective memory cell to be selected instead of the functional redundant memory cell. That is, because of the inherent delays of all electronic circuitry, a redundancy checking circuit may fail to timely recognize that an address represents a defective memory cell, and the appropriate redundant memory cells may not be activated if the operating speed of the memory device exceeds the requisite set-up time needed to ensure proper operation of the redundancy checking circuit. The alternative is to use longer set-up times, thus slowing the overall operating speed of the memory device. Accordingly, new methods and systems relating to redundancy circuitry for memory devices are desirable.